The demand for high density, highly integrated, multi-functional and high performance electronic circuits resulted in dramatic evolution of electronic device packaging, substrate design and mounting technologies.
The packaging technologies have evolved to produce finer pitch and higher pin count integrated circuits. For example, the number of leads (I/O pins) on an ASIC (application specific integrated circuit) evolved over the last few years from 800 to 1800. The leads form a pattern that occupies the entire area on the “back” of the IC; a 1.00 mm pitch is common today.
To meet the demand for packages having higher lead counts and smaller footprints, grid array packaging, such as ball grid arrays (BGAs), plastic BGAs (PBGAs), organic LAN grid arrays (OLGAs), etc, were developed. A BGA package typically has leads (or pins or I/O terminals) arranged in an array of solder balls, protruding from the bottom of the package. These terminals are soldered to a plurality of pads/balls located on the surface of the electronic substrate. Specific arrangements of power and ground leads are selected with a view to improving signal quality on signal contacts.
Printed wiring boards (PWBs), such as printed circuit boards, chip carriers or multichip modules, are well known examples of electronic substrates. PWBs usually comprise layers of conductive and dielectric materials laminated together. Some of the layers include traces or signal lines, prepared by methods well known in the art on a dielectric layer, some ground and some power planes comprised of a sheet of metal placed on a dielectric layer. The design of the PWBs evolved in parallel with the design of the ICs and electronic components. Thus, in order to accommodate the routing of ICs and components designed with a given pitch (1.27 mm, 1.00 mm, 0.8 mm or less), the distance permitted between the traces, and between the traces and the mounting pads for the ICs and components, as well as the width of the traces must decrease accordingly. Of relevance is also the design and placement of the vias and mounting pads for the ICs and the components.
Vias are formed in the PWBs to permit routing on inner layers as well as to make electrical connection between the ICs and the components mounted on the opposite side of the board. When used for mounting a component, the respective vias are provided with a pad, that ensures the electrical connection. Alternatively, a via may be connected to an adjacent ball contact pad over a short “dogbone” connection, for enabling connection to a corresponding ball on an IC or a component.
There are various types of vias. For example, the plated through hole (PTH) vias go all the way through the board. Blind vias generally go from a board surface layer through a few layers only, while the buried vias connect traces on two internal layers of the board.
It is also known that the decoupling capacitors required for high-performance operation of the electrical circuits need to be mounted as close as possible to an IC. The number of capacitors needed for proper operation of an IC increases not only with the number of circuits in the IC package, but also with the number of power and ground connections provided on the respective IC package. This is not easy, since the area under the IC is occupied by the via array used to connect the IC to the board. As many of the power and ground vias are in the middle of the array, the number of the routes within the array is limited, since the distance between the vias (pitch) of the array is very small. This problem is compounded by the increase in the number of the IC ground and power connections, as larger IC integration is achieved. Still further, the layout of the IC ground and power pins is different for different ICs, so that specific mounting solutions need to be provided for the decoupling capacitors.
As a result, various solutions are available today for mounting the BGA devices and the respective decoupling capacitors. These solutions depend on the position of the power and ground leads, pitch, the size of the area occupied by the IC device, the size of the pads on the board, the type and technology used for the vias, etc. Preferably, the decoupling capacitors are placed on the back side of the board from the IC when mounted. However, the space within the vias array on back of the board is not normally available because the vias are very close.
One solution currently being used consists of PTH (plated through hole) vias used for “Via in Pad (ViP)” solution. In this case, the vias go straight from the front to the back of the board and the capacitors are placed on the “back side” of the board. The assumption in this case is that vias cannot be depopulated and that the capacitors must be connected as close as possible to the power and ground balls. The drawbacks of this solution are that the IC is required to have the power and ground pins configured in a very specific fashion. In addition, the power and ground pins that require decoupling need to be separated by either a signal or unused pin to accommodate the size of the capacitors. This pin is covered by the body of the decoupling capacitor, so it cannot be accessed for testing. Also, the power and ground PTHs in the array must be provided with pads, leaving little space for routes; connections may not be traced between a capacitor and the adjacent unused vias. Still further, the number of decoupling capacitors that can be mounted in this way is limited since the solution requires a via row/column free between a row/column of capacitors.
Another solution currently employed in recent designs uses advanced PWB technology. This solution consists of using HDI on the PWB with the combination of blind and buried vias to allow access on the backside of the BGA component. This option provides the highest degree of freedom for the design. In this case, component pitch, pin arrangement and capacitor size do not need to be specified, since the front-to-back connection enables use of many combinations. It is also possible to maximize the number of decoupling capacitors that can fit into the available space. However, this may increase cost of the product due to potentially higher board costs.
There it is also known to provide a routing channel in the array of vias on the “back side” of the board from where the IC is mounted, as for example described in the US Patent Application Publication 2003/0183419A1 (Miller et al.), published on Oct. 2, 2003. This Patent Application discloses a pattern of columns and rows of vias, each via being associated with a pad over a short connection. The pads are arranged between the columns and the rows of vias, so that the connections form a certain angle. A routing channel is obtained between two columns (or two rows) of vias, by changing the angle of the pad in two of the two adjacent rows. For example, if the connections associated with the vias in the right column form a 45° angle with the horizontal, the connections associated with the vias in the left column will form a complementary angle of 135° angle. The channel is used, as the name indicates, for routing traces from the vias in the core of the array.
Finding new and acceptable solutions for mounting the decoupling capacitors for high performance chip package is always a struggle. As discussed, this is because of the changes in new packages using tighter pitches as well as different power and ground configurations than previous designs. Still further, the location available for mounting a decoupling capacitor is dictated by the overall configuration of the circuit layout and via configurations on a respective printed circuit board. As a result, new solutions need to be introduced as new packages are introduced.
There is a need to provide improved decoupling solutions for 1.27 mm, 1.00 mm and 0.8 mm pitch and below BGA components, which allow grid array mounting and packaging technologies to be more successfully implemented and further improved.